1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a self refresh period control circuit capable of controlling a refresh period in response to a temperature change in a manner that reduces current consumption and improves consumer reliability.
2. Description of the Background of the Invention
Semiconductor memory devices can generally be categorized as volatile memory devices and nonvolatile memory devices according to the retention or non-retention of data when an external power source is removed. Volatile memory devices include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), etc. Non-volatile memory devices include flash memory or ROM (Read Only Memory) etc. Volatile memory may be sub-categorized according to whether a recharge operation of data is required. That is, an SRAM cell is generally constructed of a flip-flop circuit and two switches, and data-static storage can be obtained by a feedback effect of the flip-flop as long as power source is applied. A DRAM cell, on the other hand, is constructed of a transistor serving as a switch and a capacitor storing data. Data storage is a result of charge accumulation in the capacitor, thus, in principle, there is no power consumption. However, leakage current is caused in a DRAM cell by a PN junction of MOS (Metal Oxide Semiconductor) transistor etc., and an initially stored charge volume is lost, thus data may be lost. To prevent loss of data, data within memory cells is read before losing data, and an initial charge volume must be again replenished in conformity with the read information. This operation is repeated periodically so as to maintain data storage. Such a recharge procedure of cell charge is referred to as a “refresh” operation.
The refresh operation can be classified according to an operating method, into an external refresh method of providing a refresh command in a DRAM controller, and a self refresh method of providing only a refresh start signal in a DRAM controller and performing a refresh operation in the device itself until a refresh completion signal is provided.
The self refresh method performs a refresh operation periodically by a period decided internally. Herewith, a re-charge period is called a refresh period and is decided by an accumulation volume in cell and by an accumulation volume and expiration time of cell.
When a computer system includes a sleep mode of operation, most of internal devices are turned off, but a semiconductor memory device such as a DRAM performs a refresh operation to continuously maintain data, and a self refresh current flows in the semiconductor memory device such as DRAM.
One of recent technology development trends is to vary the device refresh period in conformity with temperature and to reduce current consumption. That is, self refresh periods are determined respectively differently by chip internal temperature in a low power DRAM, to guarantee a refresh characteristic based on temperature and simultaneously to reduce power consumption. In such systems, temperature is divided into several regions, and at low temperatures, the period of refresh clock is lengthened relatively, so as to reduce current consumption. This is based on the known fact that that data retention time of a semiconductor memory device such as DRAM is lengthened with lowered temperature, and data retention time is relatively shorter at high temperatures than at low temperatures, thus the refresh must be performed more frequently at high operating temperatures. For that, devices are equipped with a temperature sensor, and a circuit for controlling the temperature sensor is required.
FIG. 1 is a block diagram of a conventional self refresh period control circuit employing a temperature sensor.
Referring to FIG. 1, the conventional self refresh period control circuit includes a temperature sensor part 10, a period magnification controller 20, a clock generator 30 and a refresh controller 40.
In the temperature sensor part 10, activation or deactivation of the operation is controlled in response to a clock signal MSB of the clock generator 30, and generates a period control signal TS to sense operating temperature of semiconductor memory device and select a self refresh period.
The period magnification controller 20 decides a magnification of a period clock signal TCLK applied by the clock generator 30 and outputs a refresh clock signal RS, in response to the period control signal TS.
The clock generator 30 applies a clock signal MSB having a longest period of a most significant bit(MSB) among a plurality of clock signals CLK having individually different periods, to the temperature sensor part 10, in response to a self refresh start signal SRS. Also, the clock generator 30 selects a clock signal having a predetermined period, and applies the selected period clock signal TCLK to the period magnification controller 20.
The refresh controller 40 performs a control operation to execute a refresh operation with a predetermined period in response to the refresh clock signal RS.
FIG. 2 is a detailed block diagram of the temperature sensor part 10 shown in FIG. 1.
With reference to FIG. 2, the temperature sensor part 10 of FIG. 1 includes a temperature sensor 12, an amplifier 14, a latch 16 and a sampling clock generator 18.
The sampling clock generator 18 generates a sampling clock signal SCLK in response to the clock signal MSB, the sampling clock signal SCLK having the same period as the clock signal MSB and having a relatively short low level section as compared with a high level section.
In the temperature sensor 12, an activation or deactivation of operation is controlled in response to a sampling clock signal SCLK. The temperature sensor 12 generates a temperature signal Ti indicating an operating temperature of predetermined semiconductor memory device. The temperature sensor 12 operates only in a low level section of sampling clock signal SCLK.
The amplifier 14 amplifies a temperature signal Ti of the temperature sensor 12 and outputs the amplified temperature signal TA to the latch 16.
The latch 16 receives the amplified temperature signal TA of the amplifier 14, and generates a period control signal TS for a selection of self refresh period in response to a sampling clock signal SCLK.
FIG. 3 illustrates the timing of the operation of the temperature sensor part 10 shown in FIG. 2.
The operation of the conventional self refresh period control circuit will now be described, with reference to FIGS. 1 to 3.
As shown in FIGS. 1 to 3, the clock generator 30 generates clock signals MSB and TCLK having a number of bits which are used as clock signals that control a refresh period, in response to a self refresh start signal SRS,enter. The sampling clock generator 18 generates a sampling clock signal SCLK in response to a clock signal MSB having the longest period among clock signals MSB and TCLK having a number of bits. The sampling clock signal SCLK has the same period as the clock signal MSB, but is provided as a pulse signal having a relatively short low level section, as compared with a high level section.
The temperature sensor 12 operates only in a low level section of sampling clock signal SCLK, but does not operate in a high level section. The temperature sensor 12 generates a temperature signal Ti that indicates operating temperature of a predetermined semiconductor memory device during operation. Herewith, the semiconductor memory device is provided with an installation of self refresh period control circuit.
After a refresh operation start, the temperature sensor 12 senses operating temperature of semiconductor memory device, and when the operating temperature is higher than a reference temperature, a temperature signal Ti is generated at a high level, and when lower than the reference temperature, a temperature signal Ti at a low level is generated. The temperature signal Ti is amplified by amplifier 14.
The latch 16 latches a temperature signal TA having a changed level. In other words, the latch 16 receives a temperature signal TA and latches a period control signal TS at a high level when the temperature signal TA has the high level in response to a sampling clock signal SCLK, and then, when the temperature signal TA is lowered to a low level, the period control signal TS is also lowered to a low level. The latch 16 retains the output of the temperature sensor 12, even if the temperature sensor 12 is not operating. The period control signal TS is applied to the period magnification controller 20. The latch is configured so that an initial value is determined as a high level when the initial power source is supplied.
The period magnification controller 20 decides and selects a period magnification of clock signal TCLK applied by the clock generator 30, and generates a refresh period signal RS. When the period control signal TS has a high level, a refresh period is decided in a lowest magnification, and when the period control signal TS has a low level, the refresh period is decided in a highest magnification within a range of guaranteeing a refresh characteristic of semiconductor memory device.
The refresh controller 40 performs a refresh operation in response to the refresh period signal RS. The self refresh operation is completed in response to a self refresh completion signal SRS,exit.
In the conventional self refresh period control circuit, in which the period control signal TS has a low level, and a self refresh operation is completed by a self refresh completion signal SRS,exit, and restarts by a self refresh start signal SRS,enter; before the temperature sensor 12 operates, the self refresh operation is performed on the basis of a refresh period that the period control signal TS has the low level. That is, as shown in FIG. 3, at a section II where the period control signal TS has a low level, a self refresh operation is performed on the basis of a refresh period based on low temperature, and at a section III where the period control signal TS has a high level, a self refresh is performed on the basis of a refresh period based on high temperature. In other words, at section I from the time of the generation of the self refresh start signal SRS,enter to a time prior to generation of the period control signal TS through a temperature sensing of the temperature sensor 12; a self refresh is performed by a refresh period of a previously generated period control signal TS, thus there is a problem during this time period that operation is improper for refresh characteristics based on temperature.